1. Field of the Invention
The present invention relates to a structure and method for using variable length instructions in a data processing system.
2. Description of the Prior Art
Data processing systems typically utilize instruction registers which have a fixed word boundary. This word boundary defines a fixed number of instruction bytes that can be provided to the processing system at any given time.
FIG. 1 is a schematic diagram illustrating instructions 101-103 used in a conventional data processing system (such as the Hewlett Packard HP3000 processor) having an instruction register with a fixed word boundary of four bytes. Instruction 101 is a 4-byte instruction which includes bytes A.sub.0, B.sub.0, C.sub.0 and D.sub.0. Instructions 102 and 103 are 2-byte instructions which include bytes A.sub.1, B.sub.1, A.sub.2 and B.sub.2. The HP3000 is designed to decode either 4-byte instruction 101 or 2-byte instructions 102 and 103. Such a data processing system is restricted to two instruction lengths.
FIG. 2 is a schematic diagram illustrating instructions 201-202 used in another conventional data processing system which has an instruction register with a fixed word boundary of four bytes. Such an instruction register is utilized in the XL 2067 and XL 8220 processors made by Weitek Inc. Instruction 201 is a 1-byte instruction which includes byte A.sub.0 and instruction 202 is a 3-byte instruction which include bytes A.sub.1, B.sub.l and C.sub.1. The XL 2067 and XL 8220 processors are designed to decode 1-byte instruction 201 followed by 3-byte instruction 202. Again, this processor is restricted to two instruction lengths.
FIG. 3 is a schematic diagram illustrating instructions used in a conventional data processing system which has an instruction register with a fixed word boundary of five bytes. Four-byte instruction 301, 3-byte instruction 302 and 5-byte instruction 303 are each allocated five bytes within the instruction register. Byte 304 attached to 4-byte instruction 301 and bytes 305-306 attached to 3-byte instruction 302 are not utilized. While such a processor utilizes more than two instruction lengths, it does not efficiently use all the bytes in the full allocated word boundary of the associated instruction register.
In yet other data processing systems, variable length instructions which span the fixed word boundary of the instruction register are used. FIG. 4 is a schematic diagram illustrating instructions used in another conventional data processing system which has an instruction register 400 with a fixed word boundary of eight bytes. All three bytes (A.sub.0, B.sub.0, C.sub.0) of 3-byte instruction 401, all four bytes (A.sub.1, B.sub.1, C.sub.1, D.sub.1) of 4-byte instruction 402 and the first byte (A.sub.2) of 3-byte instruction 403 are initially read into instruction register 400. The eight bytes in instruction register 400 are provided to multiplexer circuit 404. Multiplexer circuit 404 routes one of the eight bytes in instruction register to decoder circuit 406 in response to a signal provided by byte offset register 411. The signal provided by byte offset register 411 is representative of the location of the first byte of the next instruction to be decoded. Table 1 helps to illustrate the operation of the circuitry in FIG. 4.
TABLE 1 ______________________________________ Byte Offset Decoded Instruction New Byte Offset Register Byte Length Register ______________________________________ 000 A.sub.0 011 011 011 A.sub.1 100 111 111 A.sub.2 011 010 010 A.sub.3 . . . . . . ______________________________________
Initially, 3-bit byte offset register 411 is set to zero (i.e., 000). The contents of byte offset register 411 are transmitted to multiplexer circuit 404. In response, multiplexer circuit 404 routes byte A.sub.0 (from byte location 000 of instruction register 400) to decoder circuit 406 on lead 405. The length of instruction 401 is encoded in byte A.sub.0. Decoder circuit 406 decodes the length of instruction 401 (i.e., 3 bytes). The decoded length of instruction 401 is provided to adder circuit 409 on lead 408. Adder circuit 409 adds the length of instruction 401 (011) and the contents of byte offset register 411 (000) to create a summed output signal (011). This summed output signal is transmitted to byte offset register 411 on lead 410.
The contents of byte offset register 411 are again transmitted to multiplexer circuit 404. In response, multiplexer circuit 404 routes byte A.sub.1 (from byte location 011 of instruction register 400) to decoder circuit 406. Decoder circuit 406 decodes the length of instruction 402 (i.e., 4 bytes). Adder circuit 409 adds the length of instruction 402 (100) and the contents of byte offset register 411 (011) to create a new summed output signal (111). The new summed output signal is stored in byte offset register 411.
The contents of byte offset register 411 are again transmitted to multiplexer circuit 404. In response, multiplexer circuit 404 routes byte A.sub.2 (from byte location 111 of instruction register 400) to decoder circuit 406. Decoder circuit 406 decodes the length of instruction 403 (i.e., 3 bytes). Adder circuit 409 adds the length of instruction 403 (011) and the contents of byte offset register 411 (111), ignoring the carry bit, to create a new summed output signal (010). The new summed output signal is stored in byte offset register 411.
The next eight instruction bytes, which include the remaining two bytes B.sub.2, C.sub.2 of 3-byte instruction 403, are read into instruction register 400. The contents of byte offset register 411 are again transmitted to multiplexer circuit 404. In response, multiplexer circuit 404 routes byte A.sub.3 (from byte location 010 of instruction register 400) to decoder circuit 406. Decoding then continues as previously described.
While the data processing system described in connection with FIG. 4 utilizes the entire allocated fixed word boundary of instruction register 400 and allows more than two instruction lengths to be used, the additional circuitry required to locate the first byte of each instruction increases the layout area and reduces the speed of the data processing system.
It would therefore be desirable to have a data processing system which utilizes the entire allocated fixed word boundary and allows more than two instruction lengths to be used, without requiring extensive and space consuming decoding circuitry.